Advanced Nodes — Viability Meets Manufacturability

Advanced Nodes — Viability Meets Manufacturability
SEMI, San Jose, www.semi.org -- Semiconductor International, 6/6/2008
Emerging requirements for new materials, such as high-k/metal gate and capacitor dielectrics, low-k interlayer dielectrics and engineered substrates, has created the greatest period of change in semiconductor manufacturing in 30 years. At the same time, uncertainty abounds about the design flexibility, exposure tooling, cost and manufacturing integration of lithography at the 22 nm node.

“Things are changing so much faster now, in this current period, than they did for many decades,” said Intel (Santa Clara, Calif.) CTO Justin Rattner in an interview earlier this year with the Associated Press. “The pace of change is accelerating because we’re approaching a number of different physical limits at the same time.”

Overcoming these limits will be the objective of the device scaling programs at SEMICON West. From exhibitor demonstrations and new product displays to the free Device Scaling TechXPOT, meeting the challenges of Moore’s Law will be evident throughout this year’s show.

TechXPOTS are SEMICON West’s show-within-a-show concept, where perpsectives on the current and future state of technology are presented in free forums intermixed with exhibitors on the show floor. Attendees can attend the TechXPOT presentations and take the ideas and concepts directly to exhibitors for discussions about product development and implementation.

The Device Scaling TechXPOT (one of three TechXPOTS) will address the critical issues in achieving Moore’s Law, including sessions on “Advanced Processes and Materials for New Devices,” held Tuesday, July 15, from 10:30 a.m. to 1 p.m.; “Lithography for 22 nm: Will We Have a Viable Solution – and Will We Be Able to Afford it?” will be held that afternoon from 3 to 5 p.m.

The Advanced Processes session will address current and emerging requirements for new materials. This session will feature presentations by device makers, equipment manufacturers, R&D labs and materials suppliers describing new technologies and how they have been integrated into production.

Among the presentations given will be “Hi-Mobility Channels” by Prashant Majhi of the International Sematech Manufacturing Initiative (ISMI, Austin, Texas). Mobility, or the ability of a charge to move from source to drain, is one of the most active fields of research today. Many of the emerging solutions promise 10× reduction in power with 50% increase in speed, combined with better integration benefits.

Another presentation in the Advanced Processes session will cover the latest developments in the integration of III-V compounds into CMOS technology. James Fiorenza from Amber Wave (Salem, N.H.) will discuss “Ge & III-V Hetero Integration for MOSFETs.” Universities, ISMI and institutions such as IMEC (Leuven, Belgium) have been engaged in considerable research in indium antimonide, gallium arsenide, indium gallium arsenide, germanium and other III-V compounds that are expected by many to make significant inroads in as little as two years.

Atul Athalye, director of technology, electronic materials at Linde Electronics (Munich, Germany), will join the session to present “Novel Precursor Formulations & Delivery Methods for Advanced ALD Applications.” Linde has been developing new precursor formulations to broaden the materials choices for atomic layer deposition (ALD). Some of the benefits realized by Linde in high-k applications include improved process stability, higher precursor utilization, purer films and excellent process control.

The final presentation in the Advanced Processes session will come from Martin Green, leader of the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) Functional Properties Group, on “Applications of Combinatorial Methodologies to the Advanced Gate Stack.” NIST has established the National Combinatorial Methods Center (NCMC) to promote industrial adaptation of combinatorial and high-throughput measurement methods that serve to accelerate the discovery, development and optimization of innovative materials. This field is making increasing contributions to the semiconductor industry, especially in high-k/metal gate stacks.

Tuesday afternoon’s “Lithography for 22 nm” session will feature perspectives from industry experts representing design, layout, exposure tooling and manufacturing integration. The 22 nm node, expected to be reached by semiconductor companies in the 2011-2012 time frame, is likely to be achieved through double patterning using 193 nm dry or water-based immersion lithography tools. The discussion will explore whether source-mask optimization is really ready for 22 nm. Will such a complex optical solution preserve the desirable features of optical lithography (high throughput at low cost with good reliability Some observers predict the 22 nm lithography solution may present severe layout restrictions. Can our industry thrive if we take layout creativity away from designers? In this session, speakers from ASML (Veldhoven, Netherlands), Advanced Micro Devices (AMD, Sunnyvale, Calif.), Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), Carnegie Mellon University (Pittsburgh), PDF Solutions (San Jose) and Cadence Design Systems (San Jose) will share their views on the technical feasibility and financial viability of a patterning solution for 22 nm.

Materials and equipment challenges for 32 and 22 nm will also be discussed at the Device Scaling TechXPOT on Wednesday afternoon. This session will look at the next 5-8 years and address the replacement for traditional CMOS devices if traditional scaling advances prove limited. John Chen, vice president of technology at NVIDIA (Santa Clara, Calif.), will outline the performance requirements that are driving the demand for new technology. This session will feature presentations from several device makers describing the challenges they face in both logic and memory to meet these demands. Presentations from IMEC, ISMI and the Semiconductor Research Corp. (SRC, Durham, N.C.) will focus on the R&D efforts to develop the new devices, materials and technologies needed.

The morning session on Wednesday, “Advances in Device Manufacturing: Productivity, Process Control and Sustainability,” will focus on fab agility and productivity and the increased need for new metrology and process control solutions.

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